In DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory), a DLL (Delay Locked Loop) circuit for generating an internal clock synchronized with an external clock is used in order to minimize operational lag within the memory. The external clock signal must be inputted at the correct duty ratio (ratio of the high or low level of a signal in a cycle; the correct duty ratio in this case is 50%) in order for the DLL circuit to operate properly. However, a duty error of ±5% in the external clock signal is allowed by specification, and a larger duty error occurs when jitter and the like are considered. Therefore, after the duty error of the internal clock is detected by a duty detection circuit, this error must be corrected.
FIG. 9 is a simplified block diagram showing the structure of a DLL circuit.
In the DLL circuit 900 shown in FIG. 9, the external clock (CLK/CLKB) received by a clock receiver 901 is fed to a delay counter 903 through a clock controller 902, and an internal clock (RCLK/FCLK) is generated having a prescribed amount of delay. These signals are inputted to a data output unit 904 and to a duty detection circuit 906, and the duty difference is found in the duty detection circuit 906 by comparing the duty of the FLCK signal and RCLK signal. The output of a data output unit replica 905 that receives the RCLK signal is inputted to a phase comparison judgment unit 907, it is judged in the phase comparison judgment unit 907 whether the present state is ahead or delayed with respect to the external clock (CLK), and the result of this judgment is fed to a delay counter controller 908. The delay counter controller 908 controls the delay counter 903 based on the duty difference and the phase offset direction (ahead/delayed).
By this configuration, an internal clock (DQ/DQS) having no duty correction such as the one shown in FIG. 10A is outputted without modification when the DLL circuit does not have the duty detection circuit 906, but a signal in which the duty ratio is corrected to 50% (1:1) can be generated by the DLL circuit 900 having the duty detection circuit 906, as shown in FIG. 10B.
FIG. 11 is a simplified block diagram showing the structure of a conventional duty detection circuit.
As shown in FIG. 11, this duty detection circuit 200 comprises a main circuit unit 210 for receiving an RCLK signal and an FCLK signal as internal clock signals generated in the DLL circuit, and generating voltage levels (DB signal and REF signal) in accordance with the duty ratio of these internal clock signals (hereinafter referred to simply as clock signals); an amplifier 220 for amplifying the output of the main circuit unit 210; a latch circuit 230 for latching the output of the amplifier 220; a pre-charge unit 240 for charging (pre-charging) a capacitor inside the main circuit unit 210; and a transfer controller 250 for allowing discharge of a capacitor inside the main circuit unit 210. The RCLK signal in this arrangement is an internal clock signal having the same phase as the external clock signal, and the FCLK signal is an internal clock signal having the opposite phase of the external clock signal. Therefore, the RCLK signal and the FCLK signal are complementary to each other, and the term “duty ratio” is defined by the ratio at which the RCLK signal is at a high level (ratio at which the FCLK signal is at a low level).
The main circuit unit 210 comprises a capacitor C21 connected to a signal line S1; a capacitor C22 connected to a signal line S2; integration transistors Tr26 and Tr27 for receiving and switching the RCLK signal and the FCLK signal; and a bias transistor Tr28 inserted between the sources of the integration transistors Tr26 and Tr27 and the ground GND. A bias signal is fed to the bias transistor Tr28. The pre-charge unit 240 is composed of pre-charge transistors Tr21 through Tr23 for pre-charging the capacitors C21 and C22. A PreB signal for initiating pre-charging of the capacitors C21 and C22 is fed to the gates of the pre-charge transistors Tr21 through Tr23. The transfer controller 250 is composed of activation transistors Tr24 and Tr25 for allowing discharge of the capacitors C21 and C22, and an ActT signal that is an activation signal for initiating an actual integration operation is fed to the gates of the activation transistors Tr24 and Tr25.
The operation of the conventional duty detection circuit 200 will next be described with reference to FIG. 12. First, as shown in FIG. 12, when the pre-charge transistors Tr21 through Tr23 are placed in the ON state by the changing of the PreB signal to low-level, a charge is fed from the power source VDD to the capacitors C21 and C22, whereby the capacitors C21 and C22 are charged to the VDD. When the activation transistors Tr24 and Tr25 are placed in the ON state by the changing of the ActT signal to active (high-level), the charges with which the capacitors C21 and C22 were charged are alternately discharged in synchrony with the RCLK signal and FCLK signal. In other words, when the RCLK signal becomes high-level, the capacitor C21 is discharged through the activation transistor Tr24, the integration transistor Tr26, and the bias transistor Tr28; and when the FCLK signal becomes high-level, the capacitor C22 is discharged through the activation transistor Tr25, the integration transistor Tr27, and the bias transistor Tr28. Since the capacitors C21 and C22 are thereby discharged during the time period in which the RCLK signal and FCLK signal are each high-level, the potentials of the DB signal and the REF signal alternately decrease in the time period (integration operation period) in which the ActT signal is at a high level, as shown in the drawing.
The final output of the main circuit unit 210 is indicated by the potential difference between the REF signal that is the potential of the signal line S1 connected to the capacitor C21, and the DB signal that is the potential of the signal line S2 connected to the capacitor C22. The difference between these potentials is amplified by the amplifier 220, whereby a DCC signal (duty correction signal) is obtained as a 1-bit digital signal, and the DCC signal is latched in the latch circuit 230. In this arrangement, a low-level (VREF>DB) logical value for the DCC signal means that the duty ratio exceeds 50%, and a high-level (VREF<DB) logical value for the DCC signal means that the duty ratio is less than 50%. The DCC signal thus generated is fed to the delay counter controller 908 of the DLL circuit 900 described above, and the delay counter controller 908 changes the duty ratio of the clock signal based on this feedback. In other words, control is performed so that the duty ratio of the clock signal is reduced when the DCC signal is at a low level, and so that the duty ratio of the clock signal is increased when the DCC signal is at a high level. The DLL circuit causes the duty ratio of the clock signal to approach 50% by continuously performing this type of control.
The above-described conventional duty detection circuit 200 has the property that the charging level of the capacitor following removal of the charge by the integration operation fluctuates considerably according to the frequency of the clock signal. Specifically, when the clock (CLK) frequency is low, the levels of the REF signal and DB signal significantly decrease, as shown in FIG. 13A. However, as shown in FIG. 13B, the levels of the REF signal and DB signal decrease only moderately when the clock frequency is high. Drawbacks therefore occur in that the structure of the judgment circuit becomes complex when an attempt is made to adapt to such a large difference in levels.
When the duty difference of two clock signals is large, as shown in FIG. 14A, the final potential difference ΔV of the DB signal and the REF signal has a certain level after the capacitors are discharged by the integration operation. However, as shown in FIG. 14B, when there is almost no duty difference in the clock signals, the final potential difference ΔV of the DB signal and REF signal becomes extremely small. Therefore, when an attempt is made to adapt to such a minute potential difference, drawbacks occur in that a high-precision judgment circuit must be used, and the structure of the judgment circuit is complicated.
The problem of dependency on the clock frequency shown in FIG. 13 can be overcome to a certain extent by reducing the common source current or increasing the capacity of the capacitors. On the other hand, however, the problem of the output potential difference shown in FIG. 14 can be overcome to a certain extent by increasing the common source current or decreasing the capacity of the capacitors. Since the methods for overcoming the two problems described above are thus mutually exclusive, and both involve a trade-off, a new method for overcoming these problems must be found in order to achieve a high level of reconciliation between these methods.
Therefore, an object of the present invention is to provide a duty detection circuit capable of correctly operating in a wide range of frequencies without regard for the size of the duty difference; and to provide a method for controlling the same.